This description relates to managing address independent-page attributes.
Modern processors support ‘virtual memory’, which allows program instructions being executed by a CPU to refer to virtual addresses within a ‘virtual address space’ that is larger than a ‘physical address space’ that is defined by the size of main memory. Virtual memory involves address translation from one or more such virtual address spaces into a physical address space. The translation is performed using a ‘page table’ that stores mappings between virtual addresses and physical addresses at a granularity of memory pages (or simply ‘pages’).
Many modern processors also support hierarchical cache systems with multiple levels of cache, including one or more levels within the processor or within each core of a multi-core processor, and one or more levels external to the processor or cores, up to a last level cache (LLC) that is accessed just before main memory is accessed. At each level of the hierarchy, the cache stores copies of a subset of data to speed access to that data by the processor relative to the speed of a higher level cache (or relative to the speed of the main memory for the LLC). Lower level caches are closer to the processor (or core), whereas higher level caches are further away from the processor (or core). The LLC is typically shared by all of the cores of a multi-core processor. At each level, the cache system will load blocks of data into entries and evict blocks of data from entries in units of ‘cache lines’ (also called ‘cache blocks’). Each cache line includes a number of ‘words’ of data, each word consisting of a predetermined number of bytes. A memory page typically has data from many cache lines.
A technique called ‘page coloring’ (also called ‘cache coloring’) involves managing the way in which data from different memory pages are mapped to cache lines. Specifically, a particular portion of a virtual address can be associated with a particular ‘color’ such that virtual addresses with different colors are guaranteed not to overlap in a cache (e.g., by limiting each color to one or more ‘sets’ of a set associative cache).